It is conventional to fabricate a fin-shaped storage electrode node of a capacitor used in a semiconductor memory device.
This conventional technology for making a fin-shaped capacitor is shown in FIG. 1 with cross sectional views, and comprises the steps of:
in FIG. 1(A), defining isolation areas and active areas on a silicon substrate, depositing gate oxide (21) and polysilicon on them, forming a gate by patterning the gate oxide (21) and polysilicon, completing a MOS transistor by forming source/drain regions (11), and depositing a silicon nitride layer (22) layer, PA1 in FIG. 1(B), depositing a silicon oxide layer (23), a polysilicon layer (24) and silicon oxide layer (25) in cited order, forming a contact hold (30) to make a storage electrode node contact; PA1 in FIG. 1(C), depositing a polysilicon (26) layer, forming a photoresist pattern (not shown), patterning a storage electrode node by means of etching anisotropically polysilicon layers (24,26) and silicon oxide layers (23,25) with the photoresist pattern; PA1 in FIG. 1(D), forming a fin-shaped storage electrode node (8) by a wet etching of silicon oxide which has remained in a storage electrode node pattern; and PA1 in FIG. 1(E), forming a dielectric layer (27) on a storage electrode node, fabricating a capacitor in the memory cell by forming a plate electrode (10) through depositing polysilicon on a dielectric layer, depositing a silicon oxide layer (28), forming a contact hole, completing a memory cell after the formation of a bit line (18).
In this conventional process, one of the main problems is that more polysilicon-interlayer layers are needed to increase the number of fins of a storage electrode node in order to attain an ultra integrated circuit, resulting in processes and process time which are more complicated and prolonged.